IC test FAQ

When I was testing, some DC parameters had a lot of results under the same conditions. Do not understand why?

What model is the test machine you are using? What kind of product is it tested? What are the specific parameters? What is the difference?

We use the credence kalos, the test is memory, when measuring ICC, it may be from a few hundred uA - dozens of mA, the actual value should be more than ten mA.

Credence kalos I have not used it, but there are many reasons for ICC instability. If other products in the same batch do not have this problem, it may be a problem of this IC. You can do BENCHTEST first. The general initial diagnosis is to replace the test machine or use standard equipment. Comparison. Personal opinions, for references only

What does benchtest mean? There is also the same IC repeatedly testing why he is unstable.

Unstable state may be the cause of ICC instability. If the same chip test is unstable and the error is large, you can look at the following two aspects:

1. Whether the state of the chip is stable during measurement.

2. Does the chip's Input pin have FloaTIng, and the Output pin is constantly flipping?

It is to take the analog circuit test yourself, use the power supply, the oscilloscope... it is more troublesome, and you need the APPLICATION BOARD. I don't know if you have it. If it is the same instability, it will be handed over to DA or FA for analysis. CURVE TRACE first.

Is the power supply clean? Look first, if the power supply is clean. Then change the range of current to look at it, it is best to check with the sample.

The power supply is very clean, and the range should be no problem. It has a current of about 10 mA and a range of 25 mA. There should be no problem, but sometimes the current will become around 100uA. The sample is stable at around 10 mA.

If it is a MEMORY test, you can write the same data to make it not flip on the mouth. Then look at it will be better. But according to your sample, there is no problem, then there may be no solution to this problem.

More comparison

IDD (ICC) is generally a characteristic value of a device, the distribution range is not very large, and the change of 100uA-10mA is definitely abnormal.

1) If the sample is stable at around 10 mA, then there is no problem with the equipment and the test procedure. The problem of the product may be very large, and it does not need to spend a lot of brains. As Code623 said, hand it to DA/FA.

2) If there is no problem with the product, please confirm the problems with Hardware, Test Program.

-> Hardware focuses on confirming that the Relay's action is stable. You can set a breakpoint before the program Meter reads, and then keep the Strobe Meter to see if the Meter value is stable. This is to verify whether the current value is pulsing when the Hardware action is static.

-> Confirm that the Drive Pattern is normal. IDD and Pattern have a direct relationship. If the Pattern is not written properly, the DUT power consumption will be unstable.

However, if the standard sample is stable, it is not necessary to analyze the problem of the test system.

The result of handing DEVICE to DA is nothing more than confirming a bad point in the circuit or observing the curve of the curve trace. Based on the description of the landlord, it is basically certain that this product is a problem. The driving pattern and the i/o assignment should not be wrong, otherwise the standard parts will not pass.

If you want to investigate the reasons, I would like to contact the contents of semiconductor physics. The intermitent failure caused by the circuit parameter fluctuaTIon may be caused by the bombardment of the alpha particle or the internal EMI of the circuit (electromagnetic radiation, if there is an inductive device on the chip). I don't think it is necessary to involve this LEVEL in engineering.

The current solution is to ask the DA to make a report, mainly the report of benchtest and curve trace, to observe the curve characteristics of ICC/VCC under static (without relay action) conditions. It is ok to do this.

Test stability is related to the performance of your own products, test methods, and hardware (Device, Test Board).

1. Is the unstable parameter tested only VOUT? (Duty cycle, frequency? What are the other voltage conditions of VOUT?)

2. Looking for the distribution of test results, is it a big change? Or is it always too large/small?

3. What is your parameter test method? What hardware resources are used, and what are the peripheral devices of the DUT?

I don't know how you use the Test Board circuit?

Since 2576 is a switching circuit, the EMI (electromagnetic interference) problem of the test circuit is particularly important.

- The connection between the input and output should be as short as possible

- Use single point grounding

- Whether to use Schottky diode 1N5822 (or fast recovery diode). This point is often replaced by an engineer or a common rectifier/switch tube such as 1N4XXX, which causes EMI to increase and output efficiency to decrease, which is a cause of instability.

I have dealt with the LM/MC34063 before, and I also have problems with poor test stability.

Look at your pattern and power filter capacitors.

ICC should let the chip keep running, then your pattern should be loop, if the loop's end-to-end connection is not good, this problem may occur.

In addition, the tester is also a problem, you can test several DUTs repeatedly, to see if there is any law, there is no type of Pin, I/O type, if there is outside the method should check whether there is internal capacitance, charge pump Power consumption component

If it is not, it is necessary to look at the layout or processing, whether there is something short inside, this is more difficult to analyze.

That is TL431? 3PIN (TO92/8SOP) Voltage Reference, we have produced. Can you be sure to test or FAB? Is 30ea really bad, has it been verified?

Check the connection

Because there will be Handler contact resistance and Handler and Tester communication cable resistance in FT. Therefore, it is recommended to use Socket to test these Fail chips directly on Tester. If OK, check the connection.

What is the SPEC Limit?

First, when testing each die (PASS), is Vout very stable and the deviation is within +-10mv, and if so, is your CP and FT the same test system, or on the probe card of the CP? Verify a die with Socket on the DUT BOARD!

To measure all the commands, registers and stacks. Then you have to ensure that these are measurable at design time. You can access these registers and stacks through test mode. Because it is a high-speed CPU, time is not a problem, just write Pattern. People are tired.

ICC measurement instability may also be caused by self-excitation of the test module

Sometimes the sample can pass, but the chip does not pass. There are two possibilities: 1. The chip is a bit problematic, the chip itself will be self-excited; 2. The test module may also have a slight self-excitation, and the oscilloscope can be used at the output. Look at the waveform, but of course the input is not connected to the signal.

See if there are any AC components present

Although the multimeter can only measure the DC part, when testing at high speed

AC or other fluctuations have a significant impact on the test DC

It is recommended to use an oscilloscope to see if there are AC components

If there is, it is difficult to measure

Do you use the oscilloscope's AC file to see if there is any AC current? The speed should not be too fast when doing icc test, peroid = 100ns, delay 100ms after the test, it should be OK

You can set a few more sampling points (SAMPLE & AVERAGE), because your sampling point will be large on the flip edge, otherwise it may be small.

1, the problem of shading. Semiconductor devices are greatly affected by light (light effects disappear after packaging)

2. Humidity problem. If the humidity of the crystal garden test environment is abnormal, the measured parameters simply cannot explain the problem.

3, the package itself will make some drift of the parameters (central value drift or dispersion), the root cause is the environment before and after the package has changed. And semiconductor devices are closely related to the test environment.

The LM1875 is an audio power amplifier. The parameters and methods of testing are also different from those of a general-purpose op amp. It should be performed in accordance with the general power amplifier method. The test parameters can be determined according to DATASHEET, and the test circuit is also determined according to the application circuit and the test method.

Capacitive coupling is typically used on a single supply to eliminate the 1/2VCC DC offset. However, application engineers generally do not want to use this capacitor, especially in the case of HiFi, considering the distortion caused by the capacitor. So they had to use a symmetric dual power supply.

In the test, if capacitive coupling is used, THD is affected by the performance of the capacitor at least to a different extent, especially if the capacitor has a problem, the test will be wrong. Therefore, it is recommended to be able to use the best capacitors.

Will use the TL494 to control the DC 180W brush motor. Why is there noise in the initial stage of the motor, how to eliminate it? Thank you.

The IC has been 100% tested at the factory, and the chip parameters passed by the test are all within the standard value. If the conditions are not good, if it is outside the parameter list listed in the Datasheet, it is a non-conforming product (original factory shipment will not appear). Customers are too invested in chip testing, and my opinion is unnecessary. I don't know what film you are using. How can this happen?

What kind of work is FE? What kind of knowledge do you need to learn? What is the future of career development? The problem is that the landlord is Newcastle and the university ~~^_^ is convenient for the Premier League.

FE=failure analysis, a kind of DA, analysis of unqualified products, including physical observation, observation by electron microscope or optical microscope, and testing of electrical properties such as VI, IDD, etc. with BENCHTEST.

DFT (design for test design IC, one step to consider IC testability for future easy test purposes) is including: Scan Chain (a test method for sequential circuits, establishing a test inside the circuit) Loop), Boundary Scan (ibid., test loop process), Logic BIST (logic built-in test) and Memory BIST (storage circuit built-in test).

Test Pattern GeneraTIon: Deterministic Pattern, Random Pattern or ATPG (Random Graphics Vector Generated by Automated Test Vector)

Test Pattern Compression: Fault Simulation, even with MISR (MISR=multi input Shift Register).

Reaking: First question! Code631 dude, can you test the chipset?

Code631 : Chipset should not be difficult, pure LOGIC stuff.

Reaking: The North Bridge is basically a purely logical thing, but the South Bridge does not seem to be the case. And now the speed is getting faster and faster, it seems that the problem is getting more and more. Can you talk about how to understand chipset in depth?

Fuqipan1 Where can I find information such as test reports! Especially pwm! Thank you!

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