Audio decoder 567 feature overview
This article discusses phase-locked loop circuits and introduces the NE567 single-chip audio decoder IC. The tone decoding block includes a stable phase-locked loop and a transistor switch that generates a local wave when the predetermined audio is added to the input of the integrated block. This audio decoder can decode tones of various frequencies. For example, detecting a button sound of a telephone or the like. This audio decoder can also be used in BB machines, frequency monitors and controllers, precision oscillators and telemetry decoders.
This article focuses on Philip's NE567 audio decoder/phase-locked loop. This device is a 567 cheap product in an 8-pin DIP package. Figure 1 shows the package pin diagram. Figure 2 shows the internal block diagram of the device. It can be seen that the basic components of the NE567 are a phase-locked loop, a right-angle phase detector (quadrature phase detector), an amplifier, and an output transistor. The phase-locked loop contains a current-controlled oscillator (CC0), a phase detector, and a feedback filter.
Philip's NE567 has a temperature operating range of 0 to +70 °F. Its electrical characteristics are roughly the same as those of Philip's SE567, except that the SE567 has an operating temperature of -55 to 125 °F. However, 567 has been designated as an industry standard audio decoder, and several other multinational semiconductor integrated circuit manufacturers have produced this integrated block at the same time.
For example, Anal·g Device offers three AD567s, EXar offers five XR567s, and National Sevniconductor offers three LM567s. These different grades of 567 devices can work properly in the circuits discussed in this article. Therefore, such devices are collectively referred to herein as 567 audio decoders.
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The basic operating condition of the 567 is like a low voltage power switch that turns on when it receives an input tone in the selected narrow band. In other words, the 567 can be used as a sophisticated tone control switch.
The universal 567 can also be used as a variable waveform generator or a universal phase-locked loop circuit. When used as a tone control switch, the detected center frequency can be set to any value within 0.1 to 500 KHz, and the detection bandwidth can be set to any value within 14% of the center frequency. Moreover, the output switching delay can be varied over a wide time range by selecting the external resistor and capacitor.
The current-controlled 567 oscillator can change its oscillation frequency in a wide frequency band through the external resistor R1 and capacitor C1, but the signal on pin 2 can only be in a very narrow frequency band (the maximum range is about 14 free-running frequencies). %) Change its oscillation frequency. Therefore, the 567 phase-locked circuit can only be "locked" in the extremely narrow frequency band of the preset input frequency value. The integrated phase detector of 567 compares the relative frequency and phase of the input signal and the oscillator output. Only when the two signals are the same (ie, the phase-locked loop is locked) produces a stable output. The center frequency of the 567 tone switch is equal to its free-running frequency, and its bandwidth is equal to the locked range of the phase-locked loop.
Figure 3 shows the basic wiring diagram when the 567 is used as a tone switch. The input tone signal is AC coupled to pin 3 through capacitor C4, where the input impedance is approximately 20KΩ. The external output load resistor RL plugged between the positive power supply terminal and pin 8 is related to the supply voltage. The maximum supply voltage is 15V, and pin 8 can sink up to 100mA of load current.
Pin 7 is normally grounded, and pin 4 is connected to the positive supply, but its voltage value must be a minimum of 4.75V and a maximum of 9V. If you pay attention to throttling, pin 8 can also be connected to the positive supply of pin 4.
The center frequency (f0) of the oscillator is also determined by:
F0=1.1×(R1×C1)·················(1)
The unit of resistance here is KΩ, the unit of capacitance is uF, and the unit of f0 is KHz.
The equation (1) is shifted accordingly to obtain the value of the capacitor C1:
C1=1.1/(f0×R1)·················(2)
Using these two equations, the values ​​of the capacitor and the resistor can be determined, and the value of the resistor R1 should be in the range of 2 to 20 kΩ. Then, the capacitance value is determined by equation (2).
This oscillator produces an exponential sawtooth on pin 6 and a square wave on pin 5. The bandwidth of this tone switch (and the lock range of the PLL) is determined by a 3.9KΩ resistor inside C2 and 567. The output switching delay of this circuit is determined by C3 and a resistor in the integrated circuit.
Table 1 lists the electrical characteristics of Philip's NE567. All other manufacturers' different grades of 567 chips have the same characteristics as Table 1.
The peak-to-peak amplitude of this square wave is equal to the supply voltage minus 1.4V. This square wave generator and load characteristics are excellent, and any resistive load greater than 1KΩ will not affect the function of the circuit. In addition, the output of this square wave generator can also be added to a low impedance load. As shown in Figure 5, the peak current at the output of pin 8 is as high as 100 mA, but the waveform is slightly worse.
Various parameters of such an oscillator can be determined by calculating equations (1) and (2) using the aforementioned oscillation frequency and capacitance. Similarly, R1 must be limited to a range of 2 to 20 KΩ. In order to simplify the calculation and save time, the component value determining the oscillation frequency can also be directly read from the nomogram shown in FIG. 6.
For example, the 567 oscillator is required to operate at 10 kHz, and the values ​​of C1 and R1 can be 0.055 uF and 2 K Ω, or 0.0055 uF and 20 K Ω.
Adding a control voltage to pin 2 of 567 allows the oscillator's operating frequency to be fine-tuned by a few percent over a narrow range. If the control voltage is applied, pin 2 should be connected to decoupling capacitor C2, which should be approximately twice the value of C1.
Five output terminals of five outputs 567 of 567. Two of them (pins 5 and 6) provide the output waveform of the oscillator, while the third output terminal, pin 8, is the primary output of 567 as previously described. The remaining two outputs are pins 1 and 2 of this decoder.
Pin 2 is connected to the phase detector output of the phase-locked loop and is internally biased internally to 3.8V. When 567 receives the in-band input signal, the bias voltage changes, and within a typical 0.95 to 1.05 oscillator free-running frequency range, the bias voltage changes linearly with the input signal frequency. The slope is 20mV per one frequency deviation (ie 20mV/f0).
Figure 11 shows the time relationship between pin 2 output and pin 8 output when 567 is used as a tone switch. The figure shows the time relationship between the two bandwidths (14% and 7%).
Pin 1 gives the output of 567 quadrature phase detection. When the tone is locked, the average voltage on pin 1 is a function of the amplitude of the input signal within this circuit band, as shown by the transfer function of Figure 12. When the average voltage on pin 1 is pulled below the 3.8V threshold, the internal output transistor of the collector on pin 8 is turned on.
Determination of Bandwidth When 567 is used as a tone switch, its bandwidth (percentage of center frequency) has a maximum value of approximately 14%. This value is proportional to the in-band signal voltage of the 25 to 250 mV rms value. However, when the signal voltage is changed from 200 to 300 mV, the bandwidth is not affected. At the same time, the bandwidth is inversely proportional to the product of the center frequency f0 and the capacitor C2. The actual bandwidth is:
BW=1070
The unit of BW is the percentage (%) of the center frequency, and Vi ≤ 200 mVRMS. Where Vi is in units of V-RMS and C2 is in uF.
C2 is selected by trial and error processing, and the value of C2 can be selected to be twice the value of C1. The value of C2 can then be increased to reduce the bandwidth, or the value of C2 can be decreased to increase the bandwidth.
Detecting the symmetry of the bandwidth The so-called symmetry of detecting the volume is to measure the degree of symmetry between this bandwidth and the center frequency. The definition of symmetry is as follows:
(fmax+fmin-2f0)/2f
At this time, fmax and fmin are frequencies corresponding to the two edges of the detected band.
If the center frequency of a tone switch is 100 kHz and the bandwidth is 10 kHz, the edge frequency of the band is symmetrical to 95 kHz and 105 kHz, so that the symmetry is 0%. However, if the frequency band is quite asymmetrical, the edge frequencies are 100 kHz and 110 kHz, and the symmetry value is increased to 5%.
If necessary, you can use a trimmer potentiometer R2 and a 47KΩ resistor R4 to add an external trimming voltage to pin 2 of 567 to reduce the symmetry value to zero, as shown in Figure 13. Moving the middle sliding contact of the potentiometer up moves the center frequency down, and moving down increases the center frequency. Silicon diodes D1 and D2 are used for temperature compensation.
Based on the typical circuit shown in Figure 13, it is easy to design a practical tone switch. The values ​​of the frequency control element resistance R1 and the capacitance C1 can be selected using the nomogram of FIG. The choice of capacitance C2 capacity can be determined experimentally based on the above discussion. A capacitor with a capacity twice that of C1 can be used initially, and then the value can be adjusted if necessary to give the required signal bandwidth. If the symmetry of the frequency band is critical, as shown in FIG. 13, a symmetry adjustment stage is added.
Finally, the value of C3 is twice that of C2. Also check the response of this circuit. If C3 is too small, the output on pin 8 may pulse during the switching process due to the transition history. If the C3 is properly selected, the entire circuit is designed.
Any number of 567 tone switches can be fed from one audio input to form a multi-tone switch network of any desired size. Figures 14 and 15 are two practical two-stage switch networks.
The circuit in Figure 14 has the function of a two-tone decoder. A signal output can be excited when either of the two input and output signals is present. In the figure, the two tone switches are excited by a signal source, and the output is performed or not processed by a CD4001B type CMOS gate manifold. Figure 15 shows the parallel connection of two 567 tone switches, which function as a single tone switch with a relative bandwidth of 24%. In this circuit, the operating frequency of the IC1 tone switch is designed to be 1.12 times higher than the operating frequency of the IC2 tone switch. Therefore, their switching bands are superimposed.
The circuits of Figures 4 and 5 can be modified in different ways, as shown in Figures 7-10. In Figure 7, the ratio of the duty cycle or the mark/space number is completely variable for the resulting waveform, with a range of 27:1 to 1:27 by means of the trimmer potentiometer R2. In addition, in each working cycle, C1 alternately charges and discharges, charging is through the resistor R1, the left side of the diodes D1 and R2, and the discharge passes through the right side of the resistor R1, the diodes D2 and R2. Just as the mark/space ratio changes, the operating frequency changes slightly.
The circuit shown in Figure 8 can generate quadrature square waves with a 90° phase difference between the two square wave outputs on pins 5 and 8. In this circuit, input pin 3 is grounded. If a bias voltage of 2.8V or more is applied to pin 3, the square wave on pin 8 has a 180° phase shift.
9 and 10 show a circuit of an oscillator having a timing resistance value of up to about 500 kΩ. Thus, the value of the timing capacitor C1 can be scaled down. In these two circuits, there is a buffer stage indirectly at the pin 6 of 567 and the nodes of R1 and C1.
In Figure 9, this buffer stage is a primary transistor emitter follower. Unfortunately, the introduction of this level makes the symmetry of the waveform slightly worse. Correspondingly, the circuit shown in Figure 10 uses a primary op amp follower as the buffer stage. This does not affect the symmetry of the waveform.
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