New lithography tools will be essential at the 5nm node, but challenges remain in terms of film quality, impedance, and system uptime. Momentum is being applied in extreme ultraviolet (EUV) lithography, yet significant hurdles still need to be overcome before this long-anticipated technology can be widely adopted in mass production.
EUV lithography, the next major advancement for patterning nanoscale features on chips, was originally expected to launch around 2012. However, after several years of delays, the technology has been pushed further down the roadmap. Today, companies like GlobalFoundries, Intel, Samsung, and TSMC are racing to integrate EUV into their 7nm and 5nm high-volume manufacturing (HVM) processes, with varying timelines from 2018 to 2020 depending on the supplier. Meanwhile, Micron, Samsung, and SK Hynix are also exploring the use of EUV for 1xnm DRAM.
Despite these efforts, several critical components must be refined before EUV can fully enter HVM. Chipmakers must also carefully evaluate the trade-offs involved. According to recent industry data, here's a snapshot of the current EUV landscape and some key challenges:
- ASML is installing its first production-ready EUV scanner equipped with a 250-watt power source, which is expected to be completed by year-end. However, EUV uptime remains an issue.
- Impedance materials used to form patterns during exposure are still not meeting EUV specifications. While these can be adjusted, it often comes at the cost of reduced throughput. In some cases, interactions between resist and impedance can lead to process instability or failures.
- EUV films, crucial for protecting masks from contamination, are not yet ready for HVM. These thin protective layers prevent particles from damaging the mask. Without them, chipmakers may either delay production or proceed without them initially. Even so, EUV can be introduced at 7nm using advanced techniques. At 5nm and beyond, however, stricter requirements mean more time and investment will be needed to resolve these issues.
He Zhiqian, an analyst at Stifel Nicolaus, noted that while EUV is increasingly being used in mass production, the number of layers where it can be applied is still under consideration. Intel is more cautious, while Samsung is more optimistic about integrating EUV into both DRAM and logic manufacturing. He believes full HVM implementation will likely occur at TSMC’s 5nm node, possibly in 2020–2021.
OEM customers must stay ahead of the EUV curve. To help the industry gain insight, Semiconductor Engineering has examined three key areas: the EUV scanner/source, impedance, and reticle mask infrastructure.
**Why choose EUV?**
Currently, chip manufacturers rely on 193nm wavelength lithography for patterning. However, this technology reaches its limit at an 80nm pitch (40nm half-pitch). Starting at 22nm/20nm, manufacturers began using 193nm immersion lithography combined with multiple patterning techniques to reduce pitch below 40nm. This involves multiple steps of lithography, etching, and deposition, increasing costs and cycle times.
To address these challenges, the industry is turning to EUV. Although EUV is not yet ready for 7nm, it is expected to be used in later nodes. EUV is required for 5nm and beyond.
Aki Fujimura, CEO of D2S, said, “From a cost perspective, 7nm will be practical, though not ideal.†The industry hopes that as 7nm volume increases, EUV will follow the same design rules. However, 5nm really needs EUV.
Initially, EUV was targeted at 7nm contacts and vias. According to GlobalFoundries, handling these requires two to four masks per layer. With EUV, only one mask per layer is needed for 7nm and 5nm contacts and vias. According to ASML, this simplifies the process and reduces cycle time by approximately 30 days.
“This is a good compromise,†said Gary Patton, CTO at GlobalFoundries. “It doesn’t affect any design rules, so customers can benefit from shorter cycle times and better yield.â€
Early adopters plan to introduce 7nm technology using EUV between 2019 and 2020. Harry Levinson, senior researcher at GlobalFoundries, said, “We are working hard. The four major chip companies are on track for HVM in the coming years. The real question now is who will be first and who will be second.â€
**Root cause of the problem**
Before EUV can be integrated into HVM, several technical challenges must be addressed. The complexity of EUV lithography is immense.
In EUV, plasma is converted into light at a 13.5nm wavelength. This light is reflected through a series of ten multi-layer mirrors before hitting the mask. It then reflects off six more mirrors and lands on the wafer at a 6% angle.
The biggest challenge remains the power source. It currently lacks sufficient output to make EUV scanners fast enough or economically viable.
For EUV to enter HVM, scanners must generate 250 watts of power, translating to 125 wph throughput. Initially, sources only produced 10 watts. ASML has since increased output to 125 watts, boosting throughput to 85 wph.
Today, ASML is preparing the NXE:3400B EUV scanner, which has a numerical aperture of 0.33 and a resolution of 13nm. Roderik van Es, Senior Product Manager at ASML, said, “We have achieved 13nm LS and 16nm IS imaging performance.â€
The tool will initially use a 140W source with 100wph throughput. Recently, ASML demonstrated a 250W source, and the industrial version is expected to be released before year-end.
Even with a 250W source, uptime remains a concern. Current 193nm scanners operate at 250W or higher without interruption. In contrast, pre-production EUV machines have uptime around 70% to 80%.
Stifel Nicolaus’ Ho noted, “How long it takes for tools to run before downtime is still a concern, especially for Intel.†If Intel’s historical availability metrics are considered, achieving 70% or even 80% uptime would be difficult.
However, the true test will come when the NXE:3400B is deployed in the field. If uptime issues persist, manufacturers may consider purchasing additional tools for redundancy—though this is costly. Each EUV scanner costs around $125 million, compared to $70 million for today’s 193nm immersion scanners.
**Impedance problem**
For many years, the main challenge with EUV was power. Now, the focus has shifted to the process involving resist.
EUV resists fall into two categories: chemically amplified resist (CAR) and metal oxides. CAR uses a diffusion-based process, while newer metal oxide resists are based on tin oxide compounds.
Resist development involves a trade-off between resolution (R), line edge roughness (LER), and sensitivity (S). To achieve desired resolution, chipmakers want EUV resists with a sensitivity of 20mJ/cm². These resists exist but are harder to integrate into HVM than expected.
At 32nm pitch and below, regardless of dose or resist type, the industry faces challenges within reasonable ranges (<100mJ/cm²). However, resists operating at 30mJ/cm² and 40mJ/cm² have been developed. Higher doses improve resolution but reduce throughput.
At 30mJ/cm², ASML estimates the EUV scanner with a 250W source can achieve 104–105 wph, below the target of 125 wph.
Levinson said, “Existing EUV resists can support 7nm HVM, but as we move toward smaller CDs, we’re heading off a cliff.†The next node may face risks due to longer antioxidant times.
Developing resists at 20mJ/cm² is challenging. The industry is working on 5nm resists.
Resist development is tough. Richard Wise of Lam Research said, “Dose isn’t always what we want.†Due to random effects in EUV, reducing the dose presents fundamental physical challenges.
Randomness affects all lithography, but EUV is worse. “First, EUV photons carry 14 times more energy than 193nm photons. So for the same exposure dose, there are 14 times more photons,†Mike said. “Second, we’re trying to increase throughput by using low exposure doses, which means fewer photons. Fewer photons mean more random uncertainty.â€
This effect is called photon shot noise. Shot noise is the variation in the number of photons during lithography.
All types of lithography are affected, but EUV is particularly problematic. “We have higher energy photons, but not enough. That leads to wide wire roughness and line edge roughness,†said Ben Rathsack of TEL.
If that’s not enough, randomness can also cause other issues. Gregory McIntyre of Imec said, “We’ll face the first challenge in imaging for random faults like nanobridges, wire breaks, or merges.â€
Therefore, during EUV exposure, the scanner sometimes cannot resolve lines, spaces, or contacts. Or the process may cause lines to break or contacts to merge.
**Film problem**
Beyond impedance, another issue is the EUV photomask infrastructure. A photomask is the master template for an IC design. After development, it is shipped to the manufacturing facility and placed in a lithography tool. The tool projects light through the mask, creating the image on the wafer.
The industry has been producing EUV masks for years, though the process remains complex. Weston Sousa of KLA-Tencor said, “The mask industry is advancing EUV marking development. There are many challenges, from blank quality and CD uniformity to pattern defects and repairs.â€
Costs and benefits are also a concern. Barton of GlobalFoundries said, “The mask itself is flawed and defective during manufacture.â€
Recent eBeam Initiative survey data showed overall mask production at 94.8%, but EUV mask production dropped to about 64.3%.
At each node, mask defects become smaller and harder to detect. Jeff Farnsworth of Intel said, “Defect standards are looser in early cycles. Over time, they will reach HVM levels. HVM won’t be loose.â€
Samsung’s Heebom Kim noted that EUV masks are eight times more expensive than complex optical masks. But as EUV enters HVM, ASML says the cost could drop to more than three times that of optical masks.
Optical and EUV masks differ. Optical masks have an opaque chrome layer on a glass substrate. EUV masks, however, consist of 40–50 alternating layers of silicon and molybdenum on a substrate.
Mask manufacturers aim for two goals: producing defect-free EUV masks and preventing particles from landing on them. Particles from the scanner or other processes can land on the mask, causing defects that affect chip yield.
While progress is being made in making defect-free masks, preventing particle contamination is another challenge. This involves a critical part of the mask infrastructure—the protective film.
Not long ago, the industry believed EUV scanners could operate in clean environments without protective films. However, chipmakers now recognize that 100% cleanliness is not guaranteed. Without a protective film, EUV masks are prone to particles and defects.
So the industry began developing EUV protective films. Optical masks use thin polymeric materials, while ASML, the only EUV protective film supplier, has developed a polysilicon-based film just 50nm thick.
During operation, when EUV light hits the protective film, the temperature rises from 600°C to 1000°C. The problem is that the film is brittle and may degrade at these temperatures, potentially damaging the EUV mask and scanner.
ASML’s EUV protective film has been tested with a 140W EUV source, but it remains unclear how it will perform with a 250W source.
Wu Banqiu of Applied Materials said, “The EUV film has challenges in mechanical strength and application performance. It absorbs some EUV energy, causing temperature increases. The film is also in a vacuum, making natural cooling difficult.â€
In summary, the use of polysilicon films in HVM is still uncertain. As a result, the industry is adjusting its plans, considering whether to wait for HVM-grade protective films or proceed without them.
Intel said it would not go into EUV production without protective films. Farnsworth of Intel said, “We are actively studying it.â€
However, the industry is hedging its bets. Many are considering plans to enter EUV production without protective films initially.
In theory, chipmakers can handle contacts and vias without a protective film. “For those areas, there’s no need for a protective film because the critical regions are small. The risk of particles causing problems is low,†said GlobalFoundries’ Patton.
But there are consequences. Even if the EUV scanner is clean, unwanted particles can still stick to the mask.
“If we go into production without a protective film, we’ll need more mask inspection and cleaning steps,†said Levinson of GlobalFoundries. “It’s painful. We need a good protective film solution.â€
In research and development, the industry is working on the next generation of films and mask infrastructure. There is urgency in developing EUV solutions. And, of course, there is power.
Will this be achieved? Time will tell the story of EUV lithography.
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