Generally speaking, half-duplex communication is adopted for radio station communication. While one party sends a voice signal, it cannot receive the other party's voice signal. Therefore, the communication interface of the radio station is divided into two parts, one is the voice signal interface, which is used to send and receive voice, and the other is the PTT control signal interface, which is used to control the transmission and reception status of the radio station. However, at present, there are many communication devices, such as internal communications for civil aviation, maritime affairs, and railway transportation, and emergency communications. Send together to ensure the reliability of PTT control signal transmission. When the intercom device is directly connected to the radio, the interface is not compatible. Therefore, it is necessary to design a radio interface conversion module, which can separate the single frequency signal and the voice signal to realize the communication between the radio station and the intercom equipment.
Modern large-scale FPGA can not only handle the functions of the past DSP processor field, but also greatly reduce the risk and upfront cost of the application-specific integrated circuit solution. Therefore, using FPGA as the core chip and advanced digital signal processing technology to develop Come to many advantages.
1 Design principle
The FPGA-based radio interface conversion module is based on digital signal processing technology, which converts the device's voice signal into a digital signal through an analog-to-digital converter and transmits it to the input buffer. The digital voice signal is filtered by FIR (Finite Impulse Response) band rejection Filter, which filters out a known single-frequency signal, sends it to the output buffer, and converts it into a voice signal through a digital-to-analog converter, and transmits it to the radio station; on the other hand, three In step, a single frequency signal is detected, and a PTT (Push-to-Talk) control signal output is generated accordingly. The functional block diagram of its interface conversion module is shown in FIG. 1.
2 FFT processor design
The design of digital signal processing systems in Altera programmable logic devices requires development tools capable of both high-speed operations and hardware language description. Altera DSP Builder integrates these tools. Altera's DSP Builder greatly shortens the DSP development cycle. In a friendly development environment, it can help users generate a high-level hardware description language for DSP design. The FFT MegaCore funcTIon in IP is a highly parameterized fast Fourier transform process with good performance. The design uses Megacore funcTIons in the shared development platform of DSP Builder model to complete the design of FFT processor and FIR notch filter.
The design of the I / O data flow structure is as follows:
The main parameter index in the FFT MegaCore macro function module is the corresponding timing rule of the data stream. The following briefly introduces the timing principle diagram of the stream structure, as shown in Figure 2.
In Figure 2, sink_valid is the output signal of the FFT module, which indicates whether the FFT processor is ready to receive data. When both sink_ready and sink_valid are high, the FFT starts to run, wait for the sink_sop signal to be set to start inputting data, as long as either of these two signals is set to low, it means that the FFT is not ready, and the FFT will be in a waiting state until All signals are high before they start to run. Sink_sop is the start signal of one frame signal transmission, sink_eop represents the end signal of one frame signal transmission.
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