Usually C based on traditional processor is serial execution. This article introduces the difference between Xilinx Vivado-HLS based FPGA and traditional processor C compiler. For traditional software engineers, C is serial execution. This article will help software engineers understand Vviado-HLS's analysis and synthesis principle based on Xilinx FPGA.
1. Vivado-HLS FPGA parallel and processor architecture Compared to the processor architecture, the FPGA fabric has higher parallelism. Vivado-HLS is not the same as the processor compilation when compiling software C programs.
2. Vivado-HLS FPGA and processor program instruction execution For the processor, the program executes sequential instructions, such as GCC, which converts the C/C++ algorithm into an assembly language.
Such as
c = a + b
The processor converts it into assembly code as follows:
LD a, $R1
LD b, $R2
ADD $R1, $R2, $R3
ST $R3 c
It can be seen that a simple addition to the processor will require multiple assembly instruction sets to complete. As shown in the following figure, they are processor-based single and multi-instruction execution units.
The above c = a + b operation processing latency is limited by the location where the data a, b is stored, such as DDR, or hard drive.
The Vivado-HLS compiler is used to convert software C/C++ to RTL. Since the FPGA is fully parallelized, the conversion is not limited to the instruction cache and memory space.
In the above example c = a + b, Vivado-HLS integrates it into some LUTs.
The Vivado-HLS FPGA-oriented compilation instructions are processed as shown in the following figure, which is completely parallel.
Let's look at an example of multiple operations:
A[i] = B[i] * C[i];
D[i] = B[i] * E[i];
F[i] = A[i] * D[i];
The pure serial execution of the following will be used for the processor. Because arrays A, B, C, D, E, and F are stored in a single storage space, only one data can be manipulated at a time.
However, these stores are detected for Vivao-HLS and a separate memory bank is generated for each array, so that operations on arrays B, C can be performed simultaneously in parallel.
The Vivado-HLS FPGA will be executed by default as follows
Let's look at the loop operation below.
For (i=0; i<10; i++)
{
A = A + B[i] * C[i];
}
The processor's scheduling for loop iteraTIon is shown below. Serial implementation, the first loop iteraTIon ended the second loop iteraTIon.
The Vivado-HLS FPGA-based scheme for loop iteraTIon is shown below. The second loop iteration is not limited until the end of the first loop iteration. Thus, II=1 can be implemented in parallel. After the end of the first loop operation, the second loop operation can be started.
Of course, sometimes for smaller FPGA resources, Vivado-HLS can be integrated into a serial implementation similar to a processor. Summary is shown in the table below.
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